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general description the max5852 dual, 8-bit, 165msps digital-to-analog converter (dac) provides superior dynamic performance in wideband communication systems. the device inte- grates two 8-bit dac cores, and a 1.24v reference. the max5852 supports single-ended and differential modes of operation. the dynamic performance is maintained over the entire 2.7v to 3.6v power-supply operating range. the analog outputs support a -1.0v to +1.25v compliance voltage. the max5852 can operate in interleaved data mode to reduce the i/o pin count. this allows the converter to be updated on a single, 8-bit bus. the max5852 features digital control of channel gain matching to within ?.4db in sixteen 0.05db steps. channel matching improves sideband suppression in analog quadrature modulation applications. the on- chip 1.24v bandgap reference includes a control amplifier that allows external full-scale adjustments of both channels through a single resistor. the internal ref- erence can be disabled and an external reference may be applied for high-accuracy applications. the max5852 features full-scale current outputs of 2ma to 20ma and operates from a 2.7v to 3.6v single sup- ply. the dac supports three modes of power-control operation: normal, low-power standby, and complete power-down. in power-down mode, the operating current is reduced to 1?. the max5852 is packaged in a 40-pin thin qfn with exposed paddle (ep) and is specified for the extended (-40? to +85?) temperature range. pin-compatible, lower speed, and higher resolution ver- sions are also available. refer to the max5853 (10 bit, 80msps), the max5851 (8 bit, 80msps), and the max5854 (10 bit, 165msps) data sheets for more infor- mation. see table 4. applications communications vsat, lmds, mmds, wlan, point-to-point microwave links wireless base stations quadrature modulation direct digital synthesis (dds) instrumentation/ate features ? 8-bit, 165msps dual dac ? low power 190mw with i fs = 20ma at f clk = 165mhz ? 2.7v to 3.6v single supply ? full output swing and dynamic performance at 2.7v supply ? superior dynamic performance 67dbc sfdr at f out = 40mhz ? programmable channel gain matching ? integrated 1.24v low-noise bandgap reference ? single-resistor gain control ? interleaved data mode ? single-ended and differential clock input modes ? miniature 40-pin thin qfn package, 6mm x 6mm ? ev kit available?max5852 ev kit max5852 dual, 8-bit, 165msps, current-output dac ________________________________________________________________ maxim integrated products 1 ordering information 19-3232; rev 0; 4/04 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. evaluation kit available part temp range pin-package MAX5852ETL -40? to +85? 40 thin qfn-ep* 40 36 37 38 39 ep 18 21 23 22 24 25 19 20 16 17 6 5 4 3 2 1 7 8 9 10 11 12 13 14 15 26 27 28 29 30 31 32 33 34 35 n.c. db6 agnd max5852 thin qfn top view av dd outpa outna agnd outpb outnb av dd refr refo db7 db4 db5 dv dd db3 db2 dgnd db0 db1 cv dd cgnd clk cv dd clkxn clkxp dce cw n.c. n.c. n.c. da0/g0 da1/g1 da2/g2 da3/g3 da4/ren da5/ide da6/dacen da7/pd pin configuration * ep = exposed paddle.
max5852 dual, 8-bit, 165msps, current-output dac 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (av dd = dv dd = cv dd = 3v, agnd = dgnd = cgnd = 0, f dac = 165msps, differential clock, external reference, v ref = 1.2v, i fs = 20ma, output amplitude = 0db fs, differential output, t a = t min to t max , unless otherwise noted. t a +25? guaranteed by production test. t a < +25? guaranteed by design and characterization. typical values are at t a = +25?.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. av dd to agnd ...................................................... -0.3v to +4v dv dd to dgnd...................................................... -0.3v to +4v cv dd to cgnd...................................................... -0.3v to +4v av dd to dv dd .............................................................-4v to +4v av dd to cv dd .............................................................-4v to +4v dv dd to cv dd .............................................................-4v to +4v agnd to dgnd.....................................................-0.3v to +0.3v agnd to cgnd.....................................................-0.3v to +0.3v dgnd to cgnd ....................................................-0.3v to +0.3v da7?a0, db7?b0, cw , dce to dgnd ...............-0.3v to +4v clk to cgnd ..........................................-0.3v to (cv dd + 0.3v) clkxn, clkxp to cgnd.........................................-0.3v to +4v refr, refo to agnd .............................-0.3v to (av dd + 0.3v) outpa, outna to agnd ..........(av dd - 4.8v) to (av dd + 0.3v) outpb, outnb to agnd ..........(av dd - 4.8v) to (av dd + 0.3v) maximum current into any pin (excluding power supplies) ..........................................?0ma continuous power dissipation (t a = +70?) 40-pin qfn (derate 26.3mw/? above +70?) .........2105mw operating temperature range ..........................-40? to +85? storage temperature range ..............................65? to +150? junction temperature ......................................................+150? lead temperature (soldering, 10s) .................................+300? parameter symbol conditions min typ max units static performance resolution n 8 bits integral nonlinearity inl r l = 0 -0.25 ?.05 +0.25 lsb differential nonlinearity dnl guaranteed monotonic, r l = 0 -0.15 ?.05 +0.15 lsb offset error v os -0.1 ?.02 +0.1 lsb internal reference (note1) -10 ?.5 +8 gain error (see also gain error definition section) ge external reference -5.5 ?.7 +5.0 %fsr internal reference ?50 gain-error temperature drift external reference ?00 ppm/? dynamic performance f out = 10mhz 64.3 67 f out = 20mhz 66 f clk = 165mhz, a out = -1dbfs f out = 40mhz 67 f out = 10mhz 67 f out = 20mhz 67 f clk = 100mhz, a out = -1dbfs f out = 30mhz 66 spurious-free dynamic range to nyquist sfdr f clk = 25mhz, a out = -1dbfs f out = 1mhz 64 dbc f clk = 165mhz, f out = 10mhz, a out = -1dbfs, span = 10mhz 68 f clk = 100mhz, f out = 5mhz, a out = -1dbfs, span = 4mhz 70 spurious-free dynamic range within a window sfdr f clk = 25mhz, f out = 1mhz, a out = -1dbfs, span = 2mhz 67 dbc multitone power ratio to nyquist mtpr 8 tones at 400khz spacing, f clk = 78mhz, f out = 15mhz to 18.2mhz 63 dbc
max5852 dual, 8-bit, 165msps, current-output dac _______________________________________________________________________________________ 3 electrical characteristics (continued) (av dd = dv dd = cv dd = 3v, agnd = dgnd = cgnd = 0, f dac = 165msps, differential clock, external reference, v ref = 1.2v, i fs = 20ma, output amplitude = 0db fs, differential output, t a = t min to t max , unless otherwise noted. t a +25? guaranteed by production test. t a < +25? guaranteed by design and characterization. typical values are at t a = +25?.) parameter symbol conditions min typ max units multitone spurious-free dynamic range within a window 8 tones at 2.1m h z sp aci ng , f c lk = 165m h z, f ou t = 28.3m h z to 45.2m h z, sp an = 50m h z 61 dbc f out = 10mhz -71 f out = 20mhz -72 f clk = 165mhz, a out = -1dbfs f out = 40mhz -72 f out = 10mhz -71 f out = 20mhz -74 f clk = 100mhz, a out = -1dbfs f out = 30mhz -69 total harmonic distortion to nyquist (2nd- through 8th-order harmonics included) thd f clk = 25mhz, a out = -1dbfs f out = 1mhz -69 dbc output channel-to-channel isolation f out = 10mhz 90 db channel-to-channel gain mismatch f out = 10mhz, g[3:0] = 1000 0.025 db channel-to-channel phase mismatch f out = 10mhz 0.05 degrees f c lk = 165m hz, f ou t = 10m h z, i fs = 20m a 50.5 f clk = 165mhz, f out = 10mhz, i fs = 5ma 50.5 f clk = 65mhz, f out = 10mhz, i fs = 20ma 51 signal-to-noise ratio to nyquist snr f clk = 65mhz, f out = 10mhz, i fs = 5ma 51 db interleaved mode disabled, ide = 0 165 200 maximum dac conversion rate f dac interleaved mode enabled, ide = 1 82.5 100 msps glitch impulse 5 pv? output settling time t s to ?.1% error band (note 3) 12 ns output rise time 10% to 90% (note 3) 2.2 ns output fall time 90% to 10% (note 3) 2.2 ns analog output full-scale output current range i fs 220ma output voltage compliance range -1.00 +1.25 v output leakage current shutdown or standby mode -5 +5 a reference internal-reference output voltage v refo ren = 0 1.13 1.24 1.32 v
max5852 dual, 8-bit, 165msps, current-output dac 4 _______________________________________________________________________________________ electrical characteristics (continued) (av dd = dv dd = cv dd = 3v, agnd = dgnd = cgnd = 0, f dac = 165msps, differential clock, external reference, v ref = 1.2v, i fs = 20ma, output amplitude = 0db fs, differential output, t a = t min to t max , unless otherwise noted. t a +25? guaranteed by production test. t a < +25? guaranteed by design and characterization. typical values are at t a = +25?.) parameter symbol conditions min typ max units internal-reference supply rejection av dd varied from 2.7v to 3.6v 0.5 mv/v internal-reference output- voltage temperature drift tcv refo ren = 0 ?0 ppm/? internal-reference output drive capability ren = 0 50 a external-reference input voltage range ren = 1 0.10 1.2 1.32 v current gain i fs /i ref 32 ma/ma logic inputs (da7?a0, db7?b0, cw ) digital input-voltage high v ih 0.65 x dv dd v digital input-voltage low v il 0.3 x dv dd v digital input current i in -1 +1 ? digital input capacitance c in 3pf single-ended clock input/output and dce input (clk, dce ) digital input-voltage high v ih dce = 1 0.65 x cv dd v digital input-voltage low v il dce = 1 0.3 x cv dd v digital input current i in dce = 1 -1 +1 a digital input capacitance c in dce = 1 3 pf digital output-voltage high v oh dce = 0, i source = 0.5ma, figure 1 0.9 x cv dd v digital output-voltage low v ol dce = 0, i sink = 0.5ma, figure 1 0.1 x cv dd v differential clock inputs (clkxp/clkxn) differential clock input internal bias cv dd /2 v differential clock input swing 0.5 v clock input impedance measured single ended 5 k ? power requirements analog power-supply voltage av dd 2.7 3 3.6 v digital power-supply voltage dv dd 2.7 3 3.6 v clock power-supply voltage cv dd 2.7 3 3.6 v
max5852 dual, 8-bit, 165msps, current-output dac _______________________________________________________________________________________ 5 electrical characteristics (continued) (av dd = dv dd = cv dd = 3v, agnd = dgnd = cgnd = 0, f dac = 165msps, differential clock, external reference, v ref = 1.2v, i fs = 20ma, output amplitude = 0db fs, differential output, t a = t min to t max , unless otherwise noted. t a +25? guaranteed by production test. t a < +25? guaranteed by design and characterization. typical values are at t a = +25?.) parameter symbol conditions min typ max units i fs = 20ma, single-ended clock mode 43.2 46 i fs = 20ma, differential clock mode 43.2 i fs = 2ma, single-ended clock mode 5 analog supply current (note 2) i avdd i fs = 2ma, differential clock mode 5 ma i fs = 20ma, single-ended clock mode 6 6.9 digital supply current (note 2) i dvdd i fs = 20ma, differential clock mode 6 ma single-ended clock mode ( dce = 1) 13.8 16.5 clock supply current (note 2) i cvdd differential clock mode ( dce = 0) 23.7 ma total standby current i standby i avdd + i dvdd + i cvdd 3.1 3.7 ma total shutdown current i shdn i avdd + i dvdd + i cvdd 1a i fs = 20ma 190 209 single-ended clock mode ( dce = 1) i fs = 2ma 74 i fs = 20ma 219 differential clock mode ( dce = 0) i fs = 2ma 104 standby 9.3 11.1 total power dissipation (note 2) p tot shutdown 0.003 mw timing characteristics (figure 5, figure 6) propagation delay 1 clock cycles single-ended clock mode ( dce = 1) 1.2 dac data to clk rise/fall setup time (note 4) t dcs differential clock mode ( dce = 0) 2.7 ns single-ended clock mode ( dce = 1) 0.8 dac data to clk rise/fall hold time (note 4) t dch differential clock mode ( dce = 0) -0.5 ns control word to cw rise setup time t cs 2.5 ns control word to cw rise hold time t cw 2.5 ns cw high time t cwh 5ns cw low time t cwl 5ns dacen = 1 to v out stable time (coming out of standby) t stb 3s
max5852 dual, 8-bit, 165msps, current-output dac 6 _______________________________________________________________________________________ electrical characteristics (continued) (av dd = dv dd = cv dd = 3v, agnd = dgnd = cgnd = 0, f dac = 165msps, differential clock, external reference, v ref = 1.2v, i fs = 20ma, output amplitude = 0db fs, differential output, t a = t min to t max , unless otherwise noted. t a +25? guaranteed by production test. t a < +25? guaranteed by design and characterization. typical values are at t a = +25?.) parameter symbol conditions min typ max units pd = 0 to v out stable time (coming out of power-down) t shdn 500 ? maximum clock frequency at clkxp/clkxn input f clk 165 200 mhz clock high time t cxh clkxp or clkxn input 1.5 ns clock low time t cxl clkxp or clkxn input 1.5 ns clkxp rise to clk output rise delay t cdh dce = 0 2.7 ns clkxp fall to clk output fall delay t cdl dce = 0 2.7 ns note 1: including the internal reference voltage tolerance and reference amplifier offset. note 2: f dac = 165msps, f out = 10mhz. note 3: measured single-ended with 50 ? load and complementary output connected to agnd. note 4: guaranteed by design, not production tested. to output pin 5pf 0.5ma 0.5ma 1.6v figure 1. load test circuit for clk outputs
max5852 dual, 8-bit, 165msps, current-output dac _______________________________________________________________________________________ 7 spurious-free dynamic range vs. output frequency (f clk = 165mhz) max5852 toc01 f out (mhz) sfdr (dbc) 80 70 50 60 20 30 40 10 35 40 45 50 55 60 65 70 75 80 30 090 0dbfs -6dbfs -12dbfs spurious-free dynamic range vs. output frequency (f clk = 100mhz) max5852 toc02 f out (mhz) sfdr (dbc) 45 40 30 35 10 15 20 25 5 35 40 45 50 55 60 65 70 75 80 30 050 0dbfs -6dbfs -12dbfs spurious-free dynamic range vs. output frequency (f clk = 25mhz) max5852 toc03 f out (mhz) sfdr (dbc) 12 10 6 8 4 2 35 40 45 50 55 60 65 70 75 80 30 014 0dbfs -6dbfs -12dbfs spurious-free dynamic range vs. output frequency (f clk = 200mhz) max5852 toc04 f out (mhz) sfdr (dbc) 90 80 60 70 20 30 40 50 10 35 40 45 50 55 60 65 70 75 80 30 0 100 0dbfs -6dbfs -12dbfs spurious-free dynamic range vs. output frequency (f clk = 165mhz) max5852 toc05 f out (mhz) sfdr (dbc) 80 70 50 60 20 30 40 10 35 40 45 50 55 60 65 70 75 80 30 090 i fs = 10ma i fs = 20ma i fs = 5ma spurious-free dynamic range vs. output frequency (f clk = 165mhz) max5852 toc06 f out (mhz) sfdr (dbc) 80 70 50 60 20 30 40 10 35 40 45 50 55 60 65 70 75 80 30 090 av dd = dv dd = cv dd = 3.6v av dd = dv dd = cv dd = 3.3v av dd = dv dd = cv dd = 2.7v av dd = dv dd = cv dd = 3v spurious-free dynamic range vs. temperature (f clk = 165mhz) max5852 toc07 temperature ( c) sfdr (dbc) 60 35 10 -15 35 40 45 50 55 60 65 70 75 80 30 -40 85 two-tone intermodulation distortion (f clk = 165mhz, 2.5mhz window) max5852 toc08 f out (mhz) amplitude (dbm) 5.7 5.1 4.5 3.9 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 -100 3.6 6.0 f out1 = 4.8541mhz, f out2 = 5.0555mhz f out2 f out1 2f out1 - f out2 2f out2 - f out1 4.2 4.8 5.4 t ypical operating characteristics (av dd = dv dd = cv dd = 3v, agnd = dgnd = cgnd = 0, external reference, differential clock, i fs = 20ma, differential output, t a = +25?, unless otherwise noted.)
max5852 dual, 8-bit, 165msps, current-output dac 8 _______________________________________________________________________________________ t ypical operating characteristics (continued) (av dd = dv dd = cv dd = 3v, agnd = dgnd = cgnd = 0, external reference, differential clock, i fs = 20ma, differential output, t a = +25?, unless otherwise noted.) single-tone sfdr (f clk = 100mhz, 4mhz window) max5852 toc11 f out (mhz) amplitude (dbm) 6.3 5.8 4.8 3.8 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 -100 2.8 6.8 f out = 4.8667mhz a out = -1dbfs 5.3 4.3 3.3 single-tone sfdr (f clk = 165mhz, 10mhz window) max5852 toc10 f out (mhz) amplitude (dbm) 13 12 10 11 6789 5 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 -100 414 f out = 9.1667mhz a out = -1dbfs single-tone sfdr (f clk = 25mhz, 2mhz window) max5852 toc12 f out (mhz) amplitude (dbm) 1.7 1.3 0.9 0.5 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 -100 0.1 2.1 f out = 0.9667mhz a out = -1dbfs single-tone sfdr (f clk = 165mhz, nyquist window) max5852 toc13 f out (mhz) amplitude (dbm) 8.25mhz/div -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 -120 0.5 82.5 f out = 9.9159mhz a out = -1dbfs integral nonlinearity vs. digital input code max5852 toc14 digital input code inl (lsb) 224 192 32 64 96 128 160 -0.15 -0.10 -0.05 0 0.05 0.10 0.15 0.20 -0.20 0 256 differential nonlinearity vs. digital input code max5852 toc15 digital input code dnl (lsb) 224 192 32 64 96 128 160 -0.08 -0.05 -0.03 0 0.03 0.05 0.08 0.10 -0.10 0 256 eight-tone sfdr plot (f clk = 165mhz, 50mhz window) max5852 toc09 f out (mhz) amplitude (dbm) 51.7 41.7 31.7 21.7 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 -100 11.7 61.7 f t4 f t3 f t2 f t1 f t5 f t6 f t7 f t8 f t1 = 28.3667mhz f t2 = 30.3667mhz f t3 = 32.7001mhz f t4 = 34.5333mhz f t5 = 38.7002mhz f t6 = 41.0333mhz f t7 = 43.2000mhz f t8 = 45.3667mhz
max5852 dual, 8-bit, 165msps, current-output dac _______________________________________________________________________________________ 9 t ypical operating characteristics (continued) (av dd = dv dd = cv dd = 3v, agnd = dgnd = cgnd = 0, external reference, differential clock, i fs = 20ma, differential output, t a = +25?, unless otherwise noted.) power dissipation vs. clock frequency (f out = 10mhz, a out = 0dbfs) max5852 toc16 f clk (mhz) power dissipation (mw) 145 120 95 70 45 160 170 180 190 200 210 220 230 150 20 170 differential clock drive single-ended clock drive power dissipation vs. supply voltages (f clk = 165mhz, f out = 10mhz) max5852 toc17 supply voltages (v) power dissipation (mw) 3.45 3.30 3.15 3.00 2.85 170 180 190 200 210 220 250 240 230 260 160 2.70 3.60 differential clock drive single-ended clock drive reference voltage vs. supply voltages max5852 toc18 supply voltages (v) reference voltage (v) 3.45 3.30 3.15 3.00 2.85 1.21420 1.21440 1.21460 1.21480 1.21490 1.21400 2.70 3.60 1.21410 1.21430 1.21450 1.21470 reference voltage vs. temperature max5852 toc19 temperature ( c) reference voltage (v) 60 35 10 -15 1.206 1.208 1.210 1.212 1.214 1.216 1.218 1.220 1.204 -40 85 dynamic response rise time max5852 toc20 10ns/div 100mv/div dynamic response fall time max5852 toc21 10ns/div 100mv/div spurious-free dynamic range vs. output frequency (f clk = 165mhz) max5852 toc22 f out (mhz) sfdr (dbc) 80 70 50 60 20 30 40 10 35 40 45 50 55 60 65 70 75 80 30 090 0dbfs -6dbfs -12dbfs single-ended clock drive
max5852 dual, 8-bit, 165msps, current-output dac 10 ______________________________________________________________________________________ pin description pin name function 1 da7/pd channel a input data bit 7 (msb)/power-down 2 da6/dacen channel a input data bit 6/dac enable control 3 da5/ide channel a input data bit 5/interleaved data enable 4 da4/ ren channel a input data bit 4/reference enable. setting ren = 0 enables the internal reference. setting ren = 1 disables the internal reference. 5 da3/g3 channel a input data bit 3/channel a gain adjustment bit 3 6 da2/g2 channel a input data bit 2/channel a gain adjustment bit 2 7 da1/g1 channel a input data bit 1/channel a gain adjustment bit 1 8 da0/g0 channel a input data bit 0 (lsb)/channel a gain adjustment bit 0 9, 10, 21, 22 n.c. no connection. do not connect to these pins. 11 db7 channel b input data bit 7 (msb) 12 db6 channel b input data bit 6 13 db5 channel b input data bit 5 14 db4 channel b input data bit 4 15 db3 channel b input data bit 3 16 dv dd d i g i tal p ow er inp ut. s ee the p ow er s up p l i es, byp assi ng , d ecoup l i ng , and layout secti on for m or e d etai l s. 17 dgnd digital ground 18 db2 channel b input data bit 2 19 db1 channel b input data bit 1 20 db0 channel b input data bit 0 (lsb) 23 cw active-low control word write pulse. the control word is latched on the rising edge of cw . 24 dce active-low differential clock enable input. drive dce low to enable differential clock inputs clkxp and clkxn. drive dce high to disable the differential clock inputs and enable the single- ended clk input. 25 clkxp positive differential clock input. with dce = 0, clkxp and clkxn are enabled. with dce = 1, clkxp and clkxn are disabled. connect clkxp to cgnd when the differential clock is disabled. 26 clkxn negative differential clock input. with dce = 0, clkxp and clkxn are enabled. with dce = 1, clkxp and clkxn are disabled. connect clkxn to cv dd when the differential clock is disabled. 27, 30 cv dd clock power input. see the power supplies, bypassing, decoupling, and layout section for more details. 28 clk single-ended clock input/output. with the differential clock disabled ( dce = 1), clk becomes a single- ended conversion clock input. with the differential clock enabled ( dce = 0), clk is a single-ended output that mirrors differential clock inputs clkxp and clkxn. see the clock modes section for more information on clk. 29 cgnd clock ground 31 refo reference input/output. refo serves as a reference input when the internal reference is disabled. if the internal 1.24v reference is enabled, refo serves as an output for the internal reference. when the internal reference is enabled, bypass refo to agnd with a 0.1? capacitor.
detailed description the max5852 dual, high-speed, 8-bit, current-output dac provides superior performance in communication systems requiring low-distortion analog-signal recon- struction. the max5852 combines two dacs and an on- chip 1.24v reference (figure 2). the current outputs of the dacs can be configured for differential or single- ended operation. the full-scale output current range is adjustable from 2ma to 20ma to optimize power dissipa- tion and gain control. the max5852 accepts an input data and a dac con- version rate of 165mhz. the inputs are latched on the rising edge of the clock whereas the output latches on the following rising edge. the max5852 features three modes of operation: normal, standby, and power-down (table 2). these modes allow efficient power management. in power-down, the max5852 consumes only 1a of supply current. wake-up time from standby mode to normal dac operation is 3s. programming the dac an 8-bit control word routed through channel a? data port programs the gain matching, reference, and the operational mode of the max5852. the control word is latched on the rising edge of cw . cw is independent of the dac clock. the dac clock can always remain running, when the control word is written to the dac. table 1 and table 2 represent the control word format and function. the gain on channel a can be adjusted to achieve gain matching between two channels in a user? system. the gain on channel a can be adjusted from -0.4db to +0.35db in steps of 0.05db by using bits g3 to g0 (see table 3). max5852 dual, 8-bit, 165msps, current-output dac ______________________________________________________________________________________ 11 pin description (continued) pin name function 32 refr full-scale current adjustment. to set the output full-scale current, connect an external resistor rset between refr and agnd. the output full-scale current is equal to 32 x v refo /r set . 33, 39 av dd anal og p ow er inp ut. s ee the p ow er s up p l i es, byp assi ng , d ecoup l i ng , and layout secti on for m or e d etai l s. 34 outnb channel b negative analog current output 35 outpb channel b positive analog current output 36, 40 agnd analog ground 37 outna channel a negative analog current output 38 outpa channel a positive analog current output ? p exposed paddle. connect ep to the common point of all ground planes. 8-bit daca channel a gain control da0/g0 da1/g1 da2/g2 da3/g3 da5/ide da6/dacen da7/pd daca input register db0 db1 db2 db3 db4 db5 db6 db7 dacb input register control word cw g0 g1 g2 operating mode controller dacen pd g3 input data interleaver 8-bit dacb clock distribution 1.24v reference and control amplifier clock power management dce clkxp clkxn clk digital power management analog power management max5852 dv dd dgnd cv dd cgnd ide ren refr refo r set agnd outnb outpb outna outpa agnd av dd da4/ren figure 2. simplified diagram
max5852 dual, 8-bit, 165msps, current-output dac 12 ______________________________________________________________________________________ device power-up and states of operation at power-up, the max5852? default configuration is internal reference, noninterleaved input mode with a gain of 0db and a fully operational converter. in shutdown, the max5852 consumes only 1a of supply current, and in standby the current consumption is 3.1ma. wake-up time from standby mode to normal operation is 3s. clock modes the max5852 allows both single-ended cmos and dif- ferential clock mode operation, and supports update rates of up to 165msps. these modes are selected through an active-low control line called dce . in single- ended clock mode ( dce = 1), the clk pin functions as an input, which accepts a user-provided single-ended clock signal. data is written to the converter on the rising edge of the clock. the dac outputs (previous data) are updated simultaneously on the same edge. if the dce pin is pulled low, the max5852 will operate in differential clock mode. in this mode, the clock signal has to be applied to differential clock input pins clkxp/clkxn. the differential input accepts an input range of 0.5v p-p and a common-mode range of 1v to (cv dd - 0.5v), making the part ideal for low- input ampli- tude clock drives. clkxp/clkxn also help to minimize the jitter, and allow the user to connect a crystal oscillator directly to max5852. control word function pd power-down. the part enters power-down mode if pd = 1. dacen dac enable. when dacen = 0 and pd = 0, the part enters standby mode. ide interleaved data mode. ide = 1 enables the interleaved data mode. in this mode, digital data for both channels is applied through channel a in a multiplexed fashion. channel b data is written on the falling edge of the clock signal and channel a data is written on the rising edge of the clock signal. ren reference enable bit. ren = 0 activates the internal reference. ren = 1 disables the internal reference and requires the user to apply an external reference between 0.1v to 1.32v. g3 bit 3 (msb) of gain adjust word g2 bit 2 of gain adjust word g1 bit 1 of gain adjust word g0 bit 0 (lsb) of gain adjust word table 1. control word format and function mode pd dacen ide ren normal operation; noninterleaved inputs; internal reference active 01 0 0 normal operation; noninterleaved inputs; internal reference disabled 01 0 1 normal operation; interleaved inputs; internal reference disabled 01 1 1 standby 0 0 x x power-down 1 x x x power-up 0 1 x x table 2. configuration modes gain adjustment on channel a (db) g3 g2 g1 g0 +0.4 0000 0 1000 -0.35 1111 table 3. gain difference setting x = don? care. msb lsb pd dacen ide ren g3 g2 g1 g0
max5852 dual, 8-bit, 165msps, current-output dac ______________________________________________________________________________________ 13 the clk pin now becomes an output, and provides a single-ended replica of the differential clock signal, whi ch may be used to synchronize the input data. data is written to the device on the rising edge of the clk signal. internal reference and control amplifier the max5852 provides an integrated 50ppm/?, 1.24v, low-noise bandgap reference that can be disabled and overridden with an external reference voltage. refo serves either as an external reference input or an inte- grated reference output. if ren =0, the internal refer- ence is selected and refo provides a 1.24v (50?) output. buffer refo with an external amplifier, when driving a heavy load. the max5852 also employs a control amplifier designed to simultaneously regulate the full-scale out- put current (i fs ) for both outputs of the devices. calculate the output current as: i fs = 32 ? i ref where i ref is the reference output current (i ref = v refo / r set ) and i fs is the full-scale output current. r set is the reference resistor that determines the amplifier output current of the max5852 (figure 3). this current is mirrored into the current-source array where i fs is equally distributed between matched current seg- ments and summed to valid output current readings for the dacs. external reference to disable the internal reference of the max5852, set ren = 1. apply a temperature-stable, external reference to drive the refo pin and set the full-scale output (figure 4). for improved accuracy and drift perfor- mance, choose a fixed-output voltage reference such as the 1.2v, 25ppm/? max6520 bandgap reference. detailed timing the max5852 accepts an input data and the dac con- version rate of up to 165msps. the input latches on the rising edge of the clock, whereas the output latches on the following rising edge. figure 5 depicts the write cycle of the two dacs in non- interleaved mode. the max5852 can also operate in an interleaved data mode. programming the ide bit with a high level activates this mode (tables 1 and 2). in interleaved mode, data for both dac channels is written through input port a. channel b data is written on the falling edge of the clock signal and then channel a data is written on the following rising edge of the clock signal. both dac outputs (chan- nel a and b) are updated simultaneously on the next fol- lowing rising edge of the clock. in interleaved data mode, the maximum input data rate per channel is half of the rate in noninterleaved mode. the interleaved data mode is attractive for applications where lower data rates are acceptable and interfacing on a single 8-bit bus is desired (figure 6). i fs c comp * refr i ref refo max4040 1.24v bandgap reference current- source array *compensation capacitor (c comp 100nf) optional external buffer for heavier loads max5852 i ref = v ref r set r set agnd agnd ren = 0 figure 3. setting i fs with the internal 1.24v reference and the control amplifier av dd external 1.2v reference max6520 agnd 0.1 f 10 f av dd agnd i fs refr i ref refo 1.24v bandgap reference current- source array max5852 r set agnd ren = 1 figure 4. max5852 with external reference
max5852 dual, 8-bit, 165msps, current-output dac 14 ______________________________________________________________________________________ clkxn clkxp clk output cw da0?a7 outpa outna db0?b7 outpb outnb daca - 1 dacb - 1 daca dacb daca + 1 dacb + 1 daca + 2 dacb + 2 control word xxxx daca + 3 dacb + 3 daca - 1 dacb - 1 daca dacb daca + 1 dacb + 1 daca + 2 dacb + 2 xxxx (control word data) xxxx daca + 3 dacb + 3 t cxh t cxl t cdh t cdl t dcs t dch t dcs t dch t cwl t cs t cw figure 5. timing diagram for noninterleaved data mode (ide = 0) clkxn clkxp clk output cw da0?a7 outpa outna outpb outnb t cxl t cxh t cdh t cdl t dcs t dch t dcs t dch t cs t cw t cwl daca dacb + 1 daca + 1 control word dacb + 2 daca + 2 daca - 1 dacb - 1 daca dacb daca + 1 dacb + 1 figure 6. timing diagram for interleaved data mode (ide = 1)
max5852 dual, 8-bit, 165msps, current-output dac ______________________________________________________________________________________ 15 applications information differential-to-single-ended conversion the max5852 exhibits excellent dynamic performance to synthesize a wide variety of modulation schemes, including high-order qam modulation with ofdm. figure 7 shows a typical application circuit with output transformers performing the required differential-to-sin- gle-ended signal conversion. in this configuration, the max5852 operates in differential mode, which reduces even-order harmonics, and increases the available out- put power. differential dc-coupled configuration figure 8 shows the max5852 output operating in differ- ential, dc-coupled mode. this configuration can be used in communications systems employing analog quadrature upconverters and requiring a baseband sampling, dual-channel, high-speed dac for i/q synthe- sis. in these applications, information bandwidth can extend from 10mhz down to several hundred kilohertz. dc-coupling is desirable to eliminate long discharge time constants that are problematic with large, expensive coupling capacitors. analog quadrature upconverters have a dc common-mode input requirement of typically 0.7v to 1.0v. the max5852 differential i/q outputs can maintain the desired full-scale level at the required 0.7v to 1.0v dc common-mode level when powered from a single 2.85v (5%) supply. the max5852 meets this low-power requirement with minimal reduction in dynam- ic range while eliminating the need for level-shifting resistor networks. power supplies, bypassing, decoupling, and layout grounding and power-supply decoupling strongly influ- ence the max5852 performance. unwanted digital crosstalk can couple through the input, reference, power-supply, and ground connections, which can affect dynamic specifications, like signal-to-noise ratio da0?a7 8 max5852 1/2 50 ? 100 ? 50 ? outpa outna v outa , single ended db0?b7 8 max5852 1/2 50 ? 100 ? 50 ? outpb outnb v outb , single ended cv dd dv dd av dd cgnd dgnd agnd figure 7. application with output transformer (coilcraft ttwb3010-1) performing differential-to-single-ended conversion da0?a7 8 max5852 1/2 1/2 50 ? 50 ? cv dd dv dd av dd cgnd dgnd agnd outpa outna db0?b7 8 max5852 50 ? 50 ? outpb outnb figure 8. application with dc-coupled differential outputs
max5852 dual, 8-bit, 165msps, current-output dac 16 ______________________________________________________________________________________ or spurious-free dynamic range. in addition, electro- magnetic interference (emi) can either couple into or be generated by the max5852. observe the grounding and power-supply decoupling guidelines for high- speed, high-frequency applications. follow the power- supply and filter configuration to realize optimum dynamic performance. use of a multilayer printed circuit (pc) board with sepa- rate ground and power-supply planes is recommend- ed. run high-speed signals on lines directly above the ground plane. the max5852 has separate analog and digital ground buses (agnd, cgnd, and dgnd, respectively). provide separate analog, digital, and clock ground sections on the pc board with only one point connecting the three planes. the ground connec- tion points should be located underneath the device and connected to the exposed paddle. run digital sig- nals above the digital ground plane and analog/clock signals above the analog/clock ground plane. digital signals should be kept away from sensitive analog, clock, and reference inputs. keep digital signal paths short and metal trace lengths matched to avoid propa- gation delay and data skew mismatch. the max5852 includes three separate power-supply inputs: analog (av dd ), digital (dv dd ), and clock (cv dd ). use a single linear regulator power source to branch out to three separate power-supply lines (av dd , dv dd , cv dd ) and returns (agnd, dgnd, cgnd). filter each power-supply line to the respective return line using lc filters comprising ferrite beads and 10? capacitors. filter each supply input locally with 0.1? ceramic capacitors to the respective return lines. note: to maintain the dynamic performance of the electrical characteristics , ensure the voltage differ- ence between dv dd , av dd , and cv dd does not exceed 150mv. thermal characteristics and packaging thermal resistance 40-lead thin qfn-ep: ja = 38?/w the max5852 is packaged in a 40-pin thin qfn-ep package, providing greater design flexibility, increased thermal efficiency, and optimized ac performance of the dac. the ep enables the implementation of grounding techniques, which are necessary to ensure highest performance operation. in this package, the data converter die is attached to an ep lead frame with the back of this frame exposed at the package bottom surface, facing the pc board side of the package. this allows a solid attachment of the package to the pc board with standard infrared (ir) flow soldering techniques. a specially created land pat- tern on the pc board, matching the size of the ep (4.1mm ? 4.1mm), ensures the proper attachment and grounding of the dac. designing vias* into the land area and implementing large ground planes in the pc board design allows for highest performance operation of the dac. use an array of 3 ? 3 vias ( 0.3mm diame- ter per via hole and 1.2mm pitch between via holes) for this 40-pin thin qfn-ep package (package code: t4066-1). dynamic performance parameter definitions total harmonic distortion (thd) thd is the ratio of the rms sum of all essential harmon- ics (within a nyquist window) of the input signal to the fundamental itself. this can be expressed as: where v 1 is the fundamental amplitude, and v 2 through v n are the amplitudes of the 2nd through nth order har- monics. the max5852 uses the first seven harmonics for this calculation. spurious-free dynamic range (sfdr) sfdr is the ratio of rms amplitude of the carrier fre- quency (maximum signal component) to the rms value of their next-largest spectral component. sfdr is usu- ally measured in dbc with respect to the carrier fre- quency amplitude or in dbfs with respect to the dac? full-scale range. depending on its test condition, sfdr is observed within a predefined window or to nyquist. multitone power ratio (mtpr) a series of equally spaced tones are applied to the dac with one tone removed from the center of the range. mtpr is defined as the worst-case distortion (usually a 3rd-order harmonic product of the fundamental frequen- cies), which appears as the largest spur at the frequency of the missing tone in the sequence. this test can be per- formed with any number of input tones; however, four and eight tones are among the most common test conditions for cdma- and gsm/edge-type applications. thd vvv v v n = ++ + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? log ... ... 20 2 2 3 2 4 22 1 * vias connect the land pattern to internal or external copper planes.
max5852 dual, 8-bit, 165msps, current-output dac ______________________________________________________________________________________ 17 intermodulation distortion (imd) the two-tone imd is the ratio expressed in dbc of either out- put tone to the worst 3rd-order (or higher) imd products. static performance parameter definitions integral nonlinearity (inl) integral nonlinearity (inl) is the deviation of the values on an actual transfer function from a line drawn between the end points of the transfer function, once offset and gain errors have been nullified. for a dac, the deviations are measured at every individual step. differential nonlinearity (dnl) differential nonlinearity (dnl) is the difference between an actual step height and the ideal value of 1 lsb. a dnl error specification no more negative than -1 lsb guarantees monotonic transfer function. offset error offset error is the current flowing from positive dac output when the digital input code is set to zero. offset error is expressed in lsbs. gain error a gain error is the difference between the ideal and the actual full-scale output current on the transfer curve, after nullifying the offset error. this error alters the slope of the transfer function and corresponds to the same percentage error in each step. the ideal current is defined by reference voltage at 32 x v refo / r set . settling time the settling time is the amount of time required from the start of a transition until the dac output settles to its new output value to within the converter? specified accuracy. glitch impulse a glitch is generated when a dac switches between two codes. the largest glitch is usually generated around the midscale transition, when the input pattern transitions from 011?11 to 100?00. this occurs due to timing variations between the bits. the glitch impulse is found by integrating the voltage of the glitch at the midscale transition over time. the glitch impulse is usu- ally specified in pv-s. part speed (msps) resolution max5851 80 8 bit, dual max5852 165 8 bit, dual max5853 80 10 bit, dual max5854 165 10 bit, dual table 4. part selection table chip information transistor count: 9035 process: cmos
max5852 dual, 8-bit, 165msps, current-output dac maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 18 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2004 maxim integrated products printed usa is a registered trademark of maxim integrated products. package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .) package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .) package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .) package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .) qfn thin 6x6x0.8 .eps e e l l a1 a2 a e/2 e d/2 d e2/2 e2 (ne-1) x e (nd-1) x e e d2/2 d2 b k k l c l c l c l c l e 1 2 21-0141 package outline 36, 40, 48l thin qfn, 6x6x0.8mm l1 l e 8. coplanarity applies to the exposed heat sink slug as well as the terminals. 6. nd and ne refer to the number of terminals on each d and e side respectively. 5. dimension b applies to metallized terminal and is measured between 0.25 mm and 0.30 mm from terminal tip. 4. the terminal #1 identifier and terminal numbering convention shall conform to jesd 95-1 spp-012. details of terminal #1 identifier are optional, but must be located within the zone indicated. the terminal #1 identifier may be either a mold or marked feature. 9. drawing conforms to jedec mo220, except for 0.4mm lead pitch package t4866-1. 7. depopulation is possible in a symmetrical fashion. 3. n is the total number of terminals. 2. all dimensions are in millimeters. angles are in degrees. 1. dimensioning & tolerancing conform to asme y14.5m-1994. notes: 10. warpage shall not exceed 0.10 mm. e 2 2 21-0141 package outline 36, 40, 48l thin qfn, 6x6x0.8mm

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